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Espressif Systems /ESP32-S3 /SENSITIVE /CORE_1_PIF_PMS_CONSTRAIN_14

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Interpret as CORE_1_PIF_PMS_CONSTRAIN_14

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L 0CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H 0CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L 0CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H

Description

core1 access peripherals permission configuration register 14.

Fields

CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L

RTCSlow_1 memory low region permission in world 0 for core1.
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H

RTCSlow_1 memory high region permission in world 0 for core1.
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L

RTCSlow_1 memory low region permission in world 1 for core1.
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H

RTCSlow_1 memory high region permission in world 1 for core1.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data